Generally, the mass production of integrated circuits involves the fabrication of hundreds of identical circuit patterns on a single semiconductor wafer. The semiconductor wafer is then sawed into hundreds of identical chips or dies. These integrated circuits formed on the semiconductor wafer have become increasingly more complex. Modern integrated circuits are formed as multiple layers of conductive material or interconnect layers. When multiple layers of interconnect layers are employed, the integrated circuit develops a non-planar surface topography. Non-planar surfaces cause many problems in integrated circuits. These problems include voids in the dielectric materials, variations in the depth of focus causing photolithography resolution problems, damage caused by etching due to varying film thicknesses and film heights, and reductions in yield.
These problems can be avoided by planarizing the integrated circuit layers. Specifically, the doping, masking and etching techniques performed during semiconductor processing are more accurately performed when the wafer surface is planarized. For instance, a planarized surface maintains a constant depth of focus across the surface of the wafer when exposing patterns in a photolithography emulsion. This is very desirable for producing semiconductor structures in the deep sub micron range where the depth of focus is reduced during the photolithography process. The interconnecting layers are also optimized by planarizing after each process step. In particular, planarization of each interconnect layer provides each layer with a constant thickness across the surface of the wafer. This provides continuous interconnect lines across the surface of the wafer that would otherwise be discontinuous if the surface was non-planar and replete with cavities. Further, planarizing each integrated circuit layer allow finer interconnect lines to be fabricated in a given area thus increasing the circuit density. Additionally, devices having planar structures are more easily processed because substantially no corners or edges are present on the wafer surface where resist and other residuals can remain.
The planarity of a semiconductor wafer surface can be characterized according to the geometric patterns or pattern factors associated with the wafer. If planarity on the wafer is achieved independent of these pattern factors, such that planarity is achieved across the entire wafer surface, such planarization is characterized as global planarity. On the other hand, if planarity is achieved only for a specific pattern structure on the wafer surface, whereby steps and kinks are present at larger or smaller structures on other areas of the wafer surface, such planarity is characterized as local planarity.
Generally, there are two types of global planarization techniques presently used in the art. The first technique is planarization by spin on resist or by reflowing oxide. The second technique is planarization by chemical and mechanical removal of layers by polishing (CMP).
Planarization by spin on resist essentially comprises depositing a dielectric layer over the interconnection layer to be planarized. This is followed by spinning on an organic film like photoresist or polyamide, onto the rough dielectric layer. The dielectric and photoresist layers form a composite layer which is etched back to level the surface of the wafer. This is accomplished using a reactive ion etching technique that etches the dielectric and organic layer at the same rate.
Planarization by reflowing oxide involves depositing a thin dielectric layer by chemical vapor deposition (CVD) over the interconnection layer to be planarized. The dielectric layer is then heated to a temperature which is sufficient to at least partially melt the dielectric layer to cause it to flow into and fill the gaps thereby leveling the surface.
In both the spin on resist and reflow oxide techniques, the degree of planarization depends on the reflow length of either the resist or the oxide. For structures on the wafer that are much larger than the reflow length, the thickness of the planarizing layer increases relative to the smaller structures on the wafer. These thickness deviations will be reproduced in any subsequent etch-back procedure. Thus, in order to avoid such deviations, an additional photolithography step is used to generate additional filling structures within the cavities or down features on the wafer. Consequently, the planarizing resist or oxide layers will have the same height across the wafer.
There are, however, disadvantages related to the additional photolithography step which is implemented to achieve this result. Specifically, the masks used in this additional step can become very complicated. Moreover, it is difficult to obtain the same etch rate for the fill structures and for the planarizing layer.
Planarization by chemical and mechanical polishing involves depositing a layer of material over the substrate to be planarized. A rotating planar pad is applied to the wafer and grinds the layer of material to a planar surface. A chemical-liquid polishing compound, known in the art as slurry, is applied to the pad to aid in the planarization by etching the surface during polishing. The combined chemical and mechanical action of this technique rapidly removes the elevated portions of the deposited layer of material.
Planarization via CMP, is associated with some disadvantages relating to material removal rate from place to place on the wafer. For instance, the polishing rate of large up structures is slower than the polishing rate for small up structures. Further, in the case of large down features or trenches, dishing has been observed. Thus, because of these variations, additional planarization steps must be performed in order that global planarization by CMP can be successfully achieved.
These and other related global planarization techniques are described in U.S. Pat. No. 5,212,114 entitled PROCESS FOR GLOBAL PLANARIZING OF SURFACES FOR INTEGRATED SEMICONDUCTOR CIRCUITS, issued to Grewal et al. on May 18, 1993. In particular, this patent describes a process for globally planarizing the surfaces of integrated circuits wherein a locally planarized oxide film is etched back by using a photographic technique and a planarizing auxiliary layer.
Another global planarizing technique is described in U.S. Pat. No. 5,312,512 entitled GLOBAL PLANARIZATION USING SOG AND CMP, issued to Allman et al. on May 17, 1994. This technique employs a spin on glass (SOG) and an etching operation to remove high portions of the SOG and the deposition of an insulating layer prior to a chemical mechanical polish (CMP) operation.
It is accordingly an object of the present invention to provide an improved method for global planarizing the surface of a wafer having one or more integrated circuits formed thereon, which avoids the problems associated with prior art methods.